A. Sakai, S. Yamada, T. Kariya, S. Uchiyama, H. Ikeda, H. Fujita, H. Takatani, Y. Tanaka, Y. Oizono, Y. Nabeshima, T. Sudo
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PDN characteristics of 3D-SiP with a wide-bus structure under 4k-IO operations
The 4096 bits wide-bus three-dimensional integration device using through-silicon-vias (TSVs) has been designed and fabricated as a demonstrator for power integrity such as power distribution network (PDN) impedance and simultaneous switching output (SSO) noise characteristics. Anti-resonance peak of total PDN impedance was extracted at around 80 MHz. This result was well coincident with maximum SSO noise frequency at around 75 MHz. Further, SSO noise reduction clocking named phase-shift clock has also been implemented to demonstrate the effectiveness as measurement basis.
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