{"title":"随机工艺变化对不同65nm SRAM电池拓扑结构的影响","authors":"Sumit Kansal, M. Lanuzza, P. Corsonello","doi":"10.1109/ICETET.2010.19","DOIUrl":null,"url":null,"abstract":"In this paper, the influence of random process variations on different low leakage SRAM topologies has been analyzed. This analysis was performed through extensive Monte Carlo simulations and exploiting a commercial 65 nm technology. Simulation results demonstrate that the Low Vdd SRAM cell presents the best trade-off between performances and robustness against random process variations.","PeriodicalId":175615,"journal":{"name":"2010 3rd International Conference on Emerging Trends in Engineering and Technology","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Impact of Random Process Variations on Different 65nm SRAM Cell Topologies\",\"authors\":\"Sumit Kansal, M. Lanuzza, P. Corsonello\",\"doi\":\"10.1109/ICETET.2010.19\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, the influence of random process variations on different low leakage SRAM topologies has been analyzed. This analysis was performed through extensive Monte Carlo simulations and exploiting a commercial 65 nm technology. Simulation results demonstrate that the Low Vdd SRAM cell presents the best trade-off between performances and robustness against random process variations.\",\"PeriodicalId\":175615,\"journal\":{\"name\":\"2010 3rd International Conference on Emerging Trends in Engineering and Technology\",\"volume\":\"5 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-11-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 3rd International Conference on Emerging Trends in Engineering and Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICETET.2010.19\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 3rd International Conference on Emerging Trends in Engineering and Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICETET.2010.19","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Impact of Random Process Variations on Different 65nm SRAM Cell Topologies
In this paper, the influence of random process variations on different low leakage SRAM topologies has been analyzed. This analysis was performed through extensive Monte Carlo simulations and exploiting a commercial 65 nm technology. Simulation results demonstrate that the Low Vdd SRAM cell presents the best trade-off between performances and robustness against random process variations.