{"title":"带MASH 1-1-1 ΔΣ时间数字转换器的ADPLL","authors":"Zixuan Wang, Cheng Huang, Jianhui Wu","doi":"10.1109/MELCON.2014.6820544","DOIUrl":null,"url":null,"abstract":"An all digital phase-locked loop with a frequency range of 2.35 ~ 2.55 GHz is presented. A MASH 1-1-1 ΔΣ time-digital converter is used to quantize phase errors. High resolution and third-order noise-shaping are achieved simultaneously. A digitally controlled oscillator with three-stage tuning bank is used to realize wide frequency range and high frequency resolution. A prototype integrated in 130nm CMOS process exhibits a phase noise of -122 dBc/Hz @1MHz offset at a frequency of 2.48 GHz and a power dissipation of 11 mW under a supply of 1.2 V. The core occupied 0.49 mm2 of area.","PeriodicalId":103316,"journal":{"name":"MELECON 2014 - 2014 17th IEEE Mediterranean Electrotechnical Conference","volume":"112 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"An ADPLL with a MASH 1-1-1 ΔΣ Time-digital converter\",\"authors\":\"Zixuan Wang, Cheng Huang, Jianhui Wu\",\"doi\":\"10.1109/MELCON.2014.6820544\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An all digital phase-locked loop with a frequency range of 2.35 ~ 2.55 GHz is presented. A MASH 1-1-1 ΔΣ time-digital converter is used to quantize phase errors. High resolution and third-order noise-shaping are achieved simultaneously. A digitally controlled oscillator with three-stage tuning bank is used to realize wide frequency range and high frequency resolution. A prototype integrated in 130nm CMOS process exhibits a phase noise of -122 dBc/Hz @1MHz offset at a frequency of 2.48 GHz and a power dissipation of 11 mW under a supply of 1.2 V. The core occupied 0.49 mm2 of area.\",\"PeriodicalId\":103316,\"journal\":{\"name\":\"MELECON 2014 - 2014 17th IEEE Mediterranean Electrotechnical Conference\",\"volume\":\"112 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-04-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"MELECON 2014 - 2014 17th IEEE Mediterranean Electrotechnical Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MELCON.2014.6820544\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"MELECON 2014 - 2014 17th IEEE Mediterranean Electrotechnical Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MELCON.2014.6820544","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An ADPLL with a MASH 1-1-1 ΔΣ Time-digital converter
An all digital phase-locked loop with a frequency range of 2.35 ~ 2.55 GHz is presented. A MASH 1-1-1 ΔΣ time-digital converter is used to quantize phase errors. High resolution and third-order noise-shaping are achieved simultaneously. A digitally controlled oscillator with three-stage tuning bank is used to realize wide frequency range and high frequency resolution. A prototype integrated in 130nm CMOS process exhibits a phase noise of -122 dBc/Hz @1MHz offset at a frequency of 2.48 GHz and a power dissipation of 11 mW under a supply of 1.2 V. The core occupied 0.49 mm2 of area.
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