Zulfiqar Ali, A. Arshad, U. Razzaq, S. Sana, Abdul Haseeb Ahmed, Abdullah M. Harris
{"title":"基于新的秩序滤波算法的OS-CFAR处理器的设计与实现","authors":"Zulfiqar Ali, A. Arshad, U. Razzaq, S. Sana, Abdul Haseeb Ahmed, Abdullah M. Harris","doi":"10.1109/ISSOC.2010.5625543","DOIUrl":null,"url":null,"abstract":"A novel rank order statistic calculation algorithm for OS CFAR is presented. OS CFAR gives improved performance in a multitarget environment as compared to CA CFAR. However, the computational requirements of sorting data arrays complicate its implementation. We present an algorithm to overcome this challenge by employing a rank order statistic finding algorithm coupled with the exploitation of parallelism offered by FPGAs. In this technique previously computed results are used to successively divide the data array in order to find the new rank order value. The design is tested on MTI processed data from a TA-10K air traffic control radar and is part of a single chip FPGA based radar signal processor. It is implemented on a Virtex-4SX35 FPGA using the Xilinx XtremeDSP kit.","PeriodicalId":252669,"journal":{"name":"2010 International Symposium on System on Chip","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-11-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"Design and implementation of an OS-CFAR processor based on a new rank order filtering algorithm\",\"authors\":\"Zulfiqar Ali, A. Arshad, U. Razzaq, S. Sana, Abdul Haseeb Ahmed, Abdullah M. Harris\",\"doi\":\"10.1109/ISSOC.2010.5625543\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A novel rank order statistic calculation algorithm for OS CFAR is presented. OS CFAR gives improved performance in a multitarget environment as compared to CA CFAR. However, the computational requirements of sorting data arrays complicate its implementation. We present an algorithm to overcome this challenge by employing a rank order statistic finding algorithm coupled with the exploitation of parallelism offered by FPGAs. In this technique previously computed results are used to successively divide the data array in order to find the new rank order value. The design is tested on MTI processed data from a TA-10K air traffic control radar and is part of a single chip FPGA based radar signal processor. It is implemented on a Virtex-4SX35 FPGA using the Xilinx XtremeDSP kit.\",\"PeriodicalId\":252669,\"journal\":{\"name\":\"2010 International Symposium on System on Chip\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-11-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 International Symposium on System on Chip\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSOC.2010.5625543\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 International Symposium on System on Chip","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSOC.2010.5625543","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design and implementation of an OS-CFAR processor based on a new rank order filtering algorithm
A novel rank order statistic calculation algorithm for OS CFAR is presented. OS CFAR gives improved performance in a multitarget environment as compared to CA CFAR. However, the computational requirements of sorting data arrays complicate its implementation. We present an algorithm to overcome this challenge by employing a rank order statistic finding algorithm coupled with the exploitation of parallelism offered by FPGAs. In this technique previously computed results are used to successively divide the data array in order to find the new rank order value. The design is tested on MTI processed data from a TA-10K air traffic control radar and is part of a single chip FPGA based radar signal processor. It is implemented on a Virtex-4SX35 FPGA using the Xilinx XtremeDSP kit.