25gbps背板链路频率和时域表征-测试与全波三维电磁仿真之间的相关性研究

P. Amleshi, V. Shah, Zhiping Yang, J. Mohan, T. Mukherjee
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引用次数: 8

摘要

在如此高的数据速率下设计背板链路需要考虑有源和无源元件之间的相互作用。在25 Gbps数据速率下的交互程度需要一种针对主动和被动块的协同设计方法。本文首先在频域对25gbps的背板通道进行建模,建立无源通道模型与测量结果之间的相关性。我们进一步扩展这一分析,以建立芯片测试和基于芯片的仿真之间的相关性。在本研究中,我们重点研究了以25 Gbps运行的0.6米背板通道的传输性能,并期望在多通道背板系统中具有足够隔离的TX/RX分组的串扰存在时具有类似的性能。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
25 Gbps backplane links frequency and time domain characterization - correlation study between test and full-wave 3D EM simulation
Designing backplane links at such high data rates requires the consideration of the interaction between active and passive components. The degree of interaction at 25 Gbps data rates requires a co-design approach with respect to active and passive blocks. In this paper, we start with modelling a 25 Gbps backplane channel in frequency domain and establish the correlation between results obtained from passive channel model and measurement. We further extend this analysis to establish correlation between chip test and chip-based simulation. In this study, we focus on the transmission performance of a 0.6-meter backplane channel operating at 25 Gbps, and expect similar performance in the presence of crosstalk with sufficiently isolated TX/RX grouping within the multi-lane backplane system.
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