Zhaochen Yin, Walter Audoglio, M. Grassi, P. Malcovati, E. Bonizzoni
{"title":"不同超尺度技术下强臂闩锁的性能比较","authors":"Zhaochen Yin, Walter Audoglio, M. Grassi, P. Malcovati, E. Bonizzoni","doi":"10.1109/ICECS46596.2019.8964769","DOIUrl":null,"url":null,"abstract":"This paper compares the performance achievable in different scaled technologies by analog circuits, using a strong-arm latch as an example. The performance analysis has been carried out in a 7-nm and a 16-nm FinFET technologies, and in a 28-nm FDSOI technology, considering different input signal amplitudes, input common-mode voltage levels, process corners, and temperatures. The circuit used for the comparison has been optimized for the 7-nm technology with a supply voltage of 0.9 V and a clock frequency of 1 GHz and scaled, maintaining the same transistor aspect ratio in the other technologies. In typical cases, the 7-nm technology is slower than the 16-nm technology, but it has better performance in terms of power-delay product (PDP). The 16-nm technology features lower delay when the input common-mode voltage is higher than 750 mV, but with larger PDP. The 28-nm technology in all the cases is the slowest in speed and achieves the worst PDP.","PeriodicalId":209054,"journal":{"name":"2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Performance Comparison of a Strong-Arm Latch in Different Ultra-Scaled Technologies\",\"authors\":\"Zhaochen Yin, Walter Audoglio, M. Grassi, P. Malcovati, E. Bonizzoni\",\"doi\":\"10.1109/ICECS46596.2019.8964769\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper compares the performance achievable in different scaled technologies by analog circuits, using a strong-arm latch as an example. The performance analysis has been carried out in a 7-nm and a 16-nm FinFET technologies, and in a 28-nm FDSOI technology, considering different input signal amplitudes, input common-mode voltage levels, process corners, and temperatures. The circuit used for the comparison has been optimized for the 7-nm technology with a supply voltage of 0.9 V and a clock frequency of 1 GHz and scaled, maintaining the same transistor aspect ratio in the other technologies. In typical cases, the 7-nm technology is slower than the 16-nm technology, but it has better performance in terms of power-delay product (PDP). The 16-nm technology features lower delay when the input common-mode voltage is higher than 750 mV, but with larger PDP. The 28-nm technology in all the cases is the slowest in speed and achieves the worst PDP.\",\"PeriodicalId\":209054,\"journal\":{\"name\":\"2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS)\",\"volume\":\"39 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICECS46596.2019.8964769\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECS46596.2019.8964769","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Performance Comparison of a Strong-Arm Latch in Different Ultra-Scaled Technologies
This paper compares the performance achievable in different scaled technologies by analog circuits, using a strong-arm latch as an example. The performance analysis has been carried out in a 7-nm and a 16-nm FinFET technologies, and in a 28-nm FDSOI technology, considering different input signal amplitudes, input common-mode voltage levels, process corners, and temperatures. The circuit used for the comparison has been optimized for the 7-nm technology with a supply voltage of 0.9 V and a clock frequency of 1 GHz and scaled, maintaining the same transistor aspect ratio in the other technologies. In typical cases, the 7-nm technology is slower than the 16-nm technology, but it has better performance in terms of power-delay product (PDP). The 16-nm technology features lower delay when the input common-mode voltage is higher than 750 mV, but with larger PDP. The 28-nm technology in all the cases is the slowest in speed and achieves the worst PDP.