ARUZ中晶格玻尔兹曼方法实现的性能优化

2018 25th International Conference "Mixed Design of Integrated Circuits and System" (MIXDES) Pub Date : 2018-06-01 DOI:10.23919/MIXDES.2018.8436913

G. Jablonski, J. Kupis

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引用次数: 3

摘要

本文介绍了在ARUZ(位于波兰Lodz的大规模并行fpga模拟器)上实现Lattice Boltzmann方法的性能优化。与以前的出版物相比，由于通信与计算的重叠，D2Q9晶格的性能提高了46%。所提出的方法也适用于其他基于元胞自动机的仿真。从单个ARUZ板的结果推断表明，在18块ARUZ面板上进行1080 $\pmb{\times 480}$晶格的LBM模拟将达到302 103 MLUPS(每秒百万晶格更新)的性能。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Performance Optimization of Implementation of Lattice Boltzmann Method in ARUZ

The paper presents the performance optimization of implementation of the Lattice Boltzmann method on ARUZ, a massively parallel FPGA-based simulator located in Lodz, Poland. Compared to previous publications, a performance improvement of 46% has been achieved on D2Q9 lattice due to overlapping of communication with computation. The presented approach is suitable also for other cellular automata-based simulations. Extrapolation of results from the single ARUZ board suggests, that LBM simulation of 1080 $\pmb{\times 480}$ lattice on 18 panels of ARUZ would reach the performance of 302 103 MLUPS (Million Lattice Updates per Second).

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来源期刊

2018 25th International Conference "Mixed Design of Integrated Circuits and System" (MIXDES)

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