针对高漏极电流条件优化的20v LDMOS。n-epi和p-epi哪个更好?

11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312) Pub Date : 1999-05-26 DOI:10.1109/ISPSD.1999.764049

K. Kinoshita, Y. Kawaguchi, T. Sano, A. Nakagawa

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引用次数: 10

摘要

本文讨论了n-epi衬底和p-epi衬底孰优孰优。我们提出了四个优化的20v ldmosfet，并对它们进行了比较。最佳的折衷方案是在n-epi上采用高剂量n-植入层的LDMOS，在大漏极电流条件下，其导通电阻低至17.2 m/spl Omega//spl middot/mm/sup 2/，静态击穿电压高至24.0 V，且击穿电压不会下降。当栅极电压为5v时，器件导通击穿电压为24.5 V。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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20 V LDMOS optimized for high drain current condition. Which is better, n-epi or p-epi?

This paper discusses whether n-epi or p-epi substrates are better for 20 V range LDMOSFETs. We present four optimized 20 V LDMOSFETs and compare them. The best compromise is the LDMOS on n-epi with a high dose n-implant layer which achieves a sufficiently low on-resistance of 17.2 m/spl Omega//spl middot/mm/sup 2/ and a high static breakdown voltage of 24.0 V without breakdown voltage degradation under large drain current flow conditions. The device on-state breakdown voltage for a 5 V gate voltage is 24.5 V.

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11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)

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