Analyzing the impact of TFETs for ultra-low power design applications

As Moors law is concerned, down scaling of conventional CMOS technology results in, rapidly approaching fundamental limits. Alternative device structures are constantly proposed to substitute the traditional CMOS type devices. That type of device is a Tunnel Field-Effect Transistor (TFET). TFETs have the asymmetrical source/drain doping profile and they operates as reverse-biased, gated p-i-n tunnel diodes. The on-off switching mechanism in TFETs can be achieved by the gate-voltage induced band-to-band tunnelling (BTBT) at the source-channel tunnel junction only. Where as in conventional MOSFETs, only the carriers with energy exceeding the source-channel thermal barrier will contribute the on-state current. To enhance the tunnelling current, low bandgap materials (i.e. SiGe, Ge, InGaAs, InAs) have been widely used for TFET prototype device design. The two types of III-V TFETs are used for model development, based on the double-gate & ultra-thin body structure. They are InAs homo junction TFET and GaSb-InAs near-broken gap heterojunction TFET. In, this paper we will show the silvaco TCAD simulation results for both conventional MOSFET and Tunnel field effect transistor and experimental data for GaSb-InAs near-broken gap heterojunction TFET is also shown.