H. T. Duong, N. Tran, A. Huynh, H. V. Le, E. Skafidas
{"title":"12.6 GHz锁相环120∶1分频器的设计","authors":"H. T. Duong, N. Tran, A. Huynh, H. V. Le, E. Skafidas","doi":"10.1109/AUSMS.2014.7017352","DOIUrl":null,"url":null,"abstract":"A 120:1 frequency divider in 65-nm CMOS process is proposed. As a critical part of a 12.6 GHz PLL, the divider circuit divides the 12.6 GHz signal by a factor of 120 to achieve a 105 MHz reference signal. The design includes an 8:1 analog common mode logic (CML) divider followed by a 15:1 digital frequency divider. The measurement results show that it achieves a low phase noise of -109 dBc/Hz at 1 MHz offset, and a wide locking range from 8.3 GHz to 13.9 GHz. The size of the fabricated divider is 0.3 × 0.1 mm2.","PeriodicalId":108280,"journal":{"name":"2014 1st Australian Microwave Symposium (AMS)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Design of 120∶1 frequency divider for a 12.6 GHz phase-locked loop\",\"authors\":\"H. T. Duong, N. Tran, A. Huynh, H. V. Le, E. Skafidas\",\"doi\":\"10.1109/AUSMS.2014.7017352\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 120:1 frequency divider in 65-nm CMOS process is proposed. As a critical part of a 12.6 GHz PLL, the divider circuit divides the 12.6 GHz signal by a factor of 120 to achieve a 105 MHz reference signal. The design includes an 8:1 analog common mode logic (CML) divider followed by a 15:1 digital frequency divider. The measurement results show that it achieves a low phase noise of -109 dBc/Hz at 1 MHz offset, and a wide locking range from 8.3 GHz to 13.9 GHz. The size of the fabricated divider is 0.3 × 0.1 mm2.\",\"PeriodicalId\":108280,\"journal\":{\"name\":\"2014 1st Australian Microwave Symposium (AMS)\",\"volume\":\"48 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-06-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 1st Australian Microwave Symposium (AMS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/AUSMS.2014.7017352\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 1st Australian Microwave Symposium (AMS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/AUSMS.2014.7017352","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of 120∶1 frequency divider for a 12.6 GHz phase-locked loop
A 120:1 frequency divider in 65-nm CMOS process is proposed. As a critical part of a 12.6 GHz PLL, the divider circuit divides the 12.6 GHz signal by a factor of 120 to achieve a 105 MHz reference signal. The design includes an 8:1 analog common mode logic (CML) divider followed by a 15:1 digital frequency divider. The measurement results show that it achieves a low phase noise of -109 dBc/Hz at 1 MHz offset, and a wide locking range from 8.3 GHz to 13.9 GHz. The size of the fabricated divider is 0.3 × 0.1 mm2.
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