{"title":"VLSI高精度结果评估","authors":"J. Hirase","doi":"10.1109/ATS.2002.1181679","DOIUrl":null,"url":null,"abstract":"Yield is a topic of great concern in VLSI manufacture. Still, conventional research results present only average values for the yield. The present paper discloses how the yield shows a beta distribution and how that yield can be evaluated by obtaining its cumulative probability. Furthermore, a method is introduced to calculate the systematic yield that can be obtained with relative ease even with the tester on-line. Finally, concrete examples are given where an improvement in the yield was accomplished through the use of this calculation method.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"High precision result evaluation of VLSI\",\"authors\":\"J. Hirase\",\"doi\":\"10.1109/ATS.2002.1181679\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Yield is a topic of great concern in VLSI manufacture. Still, conventional research results present only average values for the yield. The present paper discloses how the yield shows a beta distribution and how that yield can be evaluated by obtaining its cumulative probability. Furthermore, a method is introduced to calculate the systematic yield that can be obtained with relative ease even with the tester on-line. Finally, concrete examples are given where an improvement in the yield was accomplished through the use of this calculation method.\",\"PeriodicalId\":199542,\"journal\":{\"name\":\"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).\",\"volume\":\"3 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-11-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ATS.2002.1181679\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ATS.2002.1181679","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Yield is a topic of great concern in VLSI manufacture. Still, conventional research results present only average values for the yield. The present paper discloses how the yield shows a beta distribution and how that yield can be evaluated by obtaining its cumulative probability. Furthermore, a method is introduced to calculate the systematic yield that can be obtained with relative ease even with the tester on-line. Finally, concrete examples are given where an improvement in the yield was accomplished through the use of this calculation method.
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