自级联码配置在28 FDSOI模拟应用中的设计优势

2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2018-03-01 DOI:10.1109/ULIS.2018.8354768

L. d'Oliveira, M. de Souza, V. Kilchytska, D. Flandre

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引用次数: 2

摘要

本文展示了ST-Microelectronics采用28FDSOI技术的UTBB晶体管的单晶体管和自级联编码(SC)关联的SPICE模拟结果，重点介绍了模拟集成电路的设计。这一比较表明，在不影响跨导的情况下，SC关联的电压增益显著提高，特别是当具有不对称阈值电压时(不对称自级联- A-SC)。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Design benefits of self-cascode configuration for analog applications in 28 FDSOI

This paper showcases SPICE simulated results of single transistors and self-cascode (SC) associations of UTBB transistors from 28FDSOI technology by ST-Microelectronics with a focus on analog integrated circuit design. This comparison demonstrates significant improvement of the voltage gain for the SC association without compromising the transconductance, especially when featuring asymmetric threshold voltages (Asymmetric Self-Cascode — A-SC).

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来源期刊

2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)

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