用于FFT实现的VLSI延迟换向器

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1984.1156682

E. Swartzlander, W. Young, S. Joseph

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引用次数: 9

摘要

将描述用于实现数据速率高达40MHz的FFT处理器的108,000晶体管延迟/换向器电路的实现。该电路包含12288个移位寄存器级和约2000个逻辑门，采用2.5μm CMOS标准单元技术实现。

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A VLSI delay commutator for FFT implementation

The implementation of a 108,000 transistor delay/commutator circuit for realization of FFT processors achieving data rates of up to 40MHz, will be described. The circuit contains 12,288 shift register stages and about 2000 logic gates, and implemented with 2.5μm CMOS standard cell technology.

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来源期刊

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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