{"title":"LSP语音合成ASIC架构","authors":"Xingjun Wu, Yi-He Sun","doi":"10.1109/ICSICT.1995.503532","DOIUrl":null,"url":null,"abstract":"A speech synthesis ASIC based on the line spectrum pair (LSP) scheme has been designed. In this ASIC, we encoded the LSP parameters with 4-bit Differential Quantization, and designed a two's complement 12-bit fixed-point serial pipeline arithmetic operations with rounding to perform the operations of the LSP speech synthesis digital filter. Finally, we verified our design for Chinese single-syllable pronunciations and continuous speech using FPGA, and obtained good synthetic speech at low bit rate (about 2.2 kbps).","PeriodicalId":286176,"journal":{"name":"Proceedings of 4th International Conference on Solid-State and IC Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"LSP speech synthesis ASIC architecture\",\"authors\":\"Xingjun Wu, Yi-He Sun\",\"doi\":\"10.1109/ICSICT.1995.503532\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A speech synthesis ASIC based on the line spectrum pair (LSP) scheme has been designed. In this ASIC, we encoded the LSP parameters with 4-bit Differential Quantization, and designed a two's complement 12-bit fixed-point serial pipeline arithmetic operations with rounding to perform the operations of the LSP speech synthesis digital filter. Finally, we verified our design for Chinese single-syllable pronunciations and continuous speech using FPGA, and obtained good synthetic speech at low bit rate (about 2.2 kbps).\",\"PeriodicalId\":286176,\"journal\":{\"name\":\"Proceedings of 4th International Conference on Solid-State and IC Technology\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-10-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of 4th International Conference on Solid-State and IC Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICSICT.1995.503532\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 4th International Conference on Solid-State and IC Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICSICT.1995.503532","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A speech synthesis ASIC based on the line spectrum pair (LSP) scheme has been designed. In this ASIC, we encoded the LSP parameters with 4-bit Differential Quantization, and designed a two's complement 12-bit fixed-point serial pipeline arithmetic operations with rounding to perform the operations of the LSP speech synthesis digital filter. Finally, we verified our design for Chinese single-syllable pronunciations and continuous speech using FPGA, and obtained good synthetic speech at low bit rate (about 2.2 kbps).
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