Fast turn around post process yield enhancement for custom VLSI foundries

An effective fast-turnaround postprocess yield-enhancement methodology for custom VLSI which has been developed using a static random access memory (SRAM) and a test element group (TEG) yield vehicle is described. The SRAM/TEG is combined on a single chip providing a unified process-control vehicle. Several examples of visual defect classification using SRAM failure analysis and nonvisual defect characterization from the electrical test monitors are presented. Application of the methodology to yield enhancement efforts for a 1.25- mu m process is presented showing excellent correlation of SRAM and custom circuit yields with a 100* defect density reduction over a two-year period.<>