{"title":"高速网络的并行协议实现","authors":"M. Zitterbart","doi":"10.1109/ITS.1990.175609","DOIUrl":null,"url":null,"abstract":"The development of high speed networks with data rates of 100 Mbit/s and more as well as the design of advanced applications imposes new requirements on the performance of network nodes. The author describes an approach to overcome the upcoming processing bottlenecks of communication protocols. The approach is based on the use of multiprocessor architectures. Several parallel concepts inside network nodes such as pipeline and array constructs are outlined, and different memory concepts are suggested. Performance measurements of protocol implementations on transputer networks following the proposed parallel concepts indicate very promising performance results.<<ETX>>","PeriodicalId":405932,"journal":{"name":"SBT/IEEE International Symposium on Telecommunications","volume":"12 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Parallel protocol implementations for high speed networks\",\"authors\":\"M. Zitterbart\",\"doi\":\"10.1109/ITS.1990.175609\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The development of high speed networks with data rates of 100 Mbit/s and more as well as the design of advanced applications imposes new requirements on the performance of network nodes. The author describes an approach to overcome the upcoming processing bottlenecks of communication protocols. The approach is based on the use of multiprocessor architectures. Several parallel concepts inside network nodes such as pipeline and array constructs are outlined, and different memory concepts are suggested. Performance measurements of protocol implementations on transputer networks following the proposed parallel concepts indicate very promising performance results.<<ETX>>\",\"PeriodicalId\":405932,\"journal\":{\"name\":\"SBT/IEEE International Symposium on Telecommunications\",\"volume\":\"12 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-09-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"SBT/IEEE International Symposium on Telecommunications\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ITS.1990.175609\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"SBT/IEEE International Symposium on Telecommunications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ITS.1990.175609","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Parallel protocol implementations for high speed networks
The development of high speed networks with data rates of 100 Mbit/s and more as well as the design of advanced applications imposes new requirements on the performance of network nodes. The author describes an approach to overcome the upcoming processing bottlenecks of communication protocols. The approach is based on the use of multiprocessor architectures. Several parallel concepts inside network nodes such as pipeline and array constructs are outlined, and different memory concepts are suggested. Performance measurements of protocol implementations on transputer networks following the proposed parallel concepts indicate very promising performance results.<>
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