{"title":"硅光子片上光互连网络","authors":"K. Bergman","doi":"10.1109/LEOS.2007.4382483","DOIUrl":null,"url":null,"abstract":"The recent emergence of multicore processor architectures is challenging the on-chip and inter-node communications infrastructure. We present the design of a silicon photonic network-on-chip that can deliver a high-bandwidth, low-latency, and power efficient scalable solution for future chip multiprocessors.","PeriodicalId":110592,"journal":{"name":"LEOS 2007 - IEEE Lasers and Electro-Optics Society Annual Meeting Conference Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"Silicon Photonic On-Chip Optical Interconnection Networks\",\"authors\":\"K. Bergman\",\"doi\":\"10.1109/LEOS.2007.4382483\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The recent emergence of multicore processor architectures is challenging the on-chip and inter-node communications infrastructure. We present the design of a silicon photonic network-on-chip that can deliver a high-bandwidth, low-latency, and power efficient scalable solution for future chip multiprocessors.\",\"PeriodicalId\":110592,\"journal\":{\"name\":\"LEOS 2007 - IEEE Lasers and Electro-Optics Society Annual Meeting Conference Proceedings\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-11-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"LEOS 2007 - IEEE Lasers and Electro-Optics Society Annual Meeting Conference Proceedings\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/LEOS.2007.4382483\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"LEOS 2007 - IEEE Lasers and Electro-Optics Society Annual Meeting Conference Proceedings","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/LEOS.2007.4382483","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The recent emergence of multicore processor architectures is challenging the on-chip and inter-node communications infrastructure. We present the design of a silicon photonic network-on-chip that can deliver a high-bandwidth, low-latency, and power efficient scalable solution for future chip multiprocessors.