{"title":"使用高阶函数的空间/时间权衡方法","authors":"R. Wester, J. Kuper","doi":"10.1109/FPL.2013.6645613","DOIUrl":null,"url":null,"abstract":"Large digital signal processing applications like particle filtering require a tradeoff between execution time and area in order to scale on FPGAs. This research focuses on developing a methodology to make this tradeoff based on structure in the mathematical description of the application. Structure is expressed using higher-order functions which are transformed using tradeoff rules to reduce area usage on FPGA.","PeriodicalId":200435,"journal":{"name":"2013 23rd International Conference on Field programmable Logic and Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A space/time tradeoff methodology using higher-order functions\",\"authors\":\"R. Wester, J. Kuper\",\"doi\":\"10.1109/FPL.2013.6645613\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Large digital signal processing applications like particle filtering require a tradeoff between execution time and area in order to scale on FPGAs. This research focuses on developing a methodology to make this tradeoff based on structure in the mathematical description of the application. Structure is expressed using higher-order functions which are transformed using tradeoff rules to reduce area usage on FPGA.\",\"PeriodicalId\":200435,\"journal\":{\"name\":\"2013 23rd International Conference on Field programmable Logic and Applications\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-10-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 23rd International Conference on Field programmable Logic and Applications\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/FPL.2013.6645613\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 23rd International Conference on Field programmable Logic and Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/FPL.2013.6645613","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A space/time tradeoff methodology using higher-order functions
Large digital signal processing applications like particle filtering require a tradeoff between execution time and area in order to scale on FPGAs. This research focuses on developing a methodology to make this tradeoff based on structure in the mathematical description of the application. Structure is expressed using higher-order functions which are transformed using tradeoff rules to reduce area usage on FPGA.