VLSI互连信号的投影框架分析方法

2005 6th International Conference on ASIC Pub Date : 2005-10-24 DOI:10.1109/ICASIC.2005.1611477

G. Suzuki

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引用次数: 2

摘要

Elmore基极延迟计算方法已被广泛使用，但该方法不能满足当前深亚微米工艺设计的精度要求。另一方面，SPICE可以提供较高的精度，但非常耗时。为此，提出了一种新颖、高精度、高速的延迟分析方法:模型降阶法(MOR)。我们将其应用于互连信号分析，以评估其性能

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VLSI interconnect signal analysis using a projection framework method

The Elmore base delay calculation method has long been in use, but this method cannot meet accuracy demands of current designs using deep sub-micron processes. On the other hand, SPICE can provide high accuracy, but it is very time consuming. Therefore, a novel, highly accurate and high-speed delay analysis method is proposed: MOR (model order reduction). We applied it in interconnect signal analysis to evaluate its performance

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2005 6th International Conference on ASIC

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