D. Muratore, Alper Akdikmen, E. Bonizzoni, F. Maloberti, U. Chio, Sai-Weng Sin, R. Martins
{"title":"采用65nm CMOS技术的8位0.7 gs /s单通道flash-SAR ADC","authors":"D. Muratore, Alper Akdikmen, E. Bonizzoni, F. Maloberti, U. Chio, Sai-Weng Sin, R. Martins","doi":"10.1109/ESSCIRC.2016.7598331","DOIUrl":null,"url":null,"abstract":"This paper presents the prototype of a single channel 8-bit 0.7-GS/s A/D converter implemented in a 65-nm CMOS process. The required thresholds are generated from the resistive interpolation embedded within the preamplifier preceding the latches. The active area of the chip is 150 × 220 μm2 and the total power consumption is 5.96 mW. At Nyquist, the ADC achieves 6.62 ENOB, resulting in a figure of merit equal to 86.7 fJ/conversion-step.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"37 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"An 8-bit 0.7-GS/s single channel flash-SAR ADC in 65-nm CMOS technology\",\"authors\":\"D. Muratore, Alper Akdikmen, E. Bonizzoni, F. Maloberti, U. Chio, Sai-Weng Sin, R. Martins\",\"doi\":\"10.1109/ESSCIRC.2016.7598331\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the prototype of a single channel 8-bit 0.7-GS/s A/D converter implemented in a 65-nm CMOS process. The required thresholds are generated from the resistive interpolation embedded within the preamplifier preceding the latches. The active area of the chip is 150 × 220 μm2 and the total power consumption is 5.96 mW. At Nyquist, the ADC achieves 6.62 ENOB, resulting in a figure of merit equal to 86.7 fJ/conversion-step.\",\"PeriodicalId\":246471,\"journal\":{\"name\":\"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference\",\"volume\":\"37 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.2016.7598331\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2016.7598331","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8
摘要
本文介绍了一种采用65纳米CMOS工艺实现的单通道8位0.7-GS/s a /D转换器的原型。所需的阈值由嵌入在锁存器之前的前置放大器内的电阻插值产生。芯片的有效面积为150 × 220 μm2，总功耗为5.96 mW。在奈奎斯特，ADC达到6.62 ENOB，其优点等于86.7 fJ/转换步长。
An 8-bit 0.7-GS/s single channel flash-SAR ADC in 65-nm CMOS technology
This paper presents the prototype of a single channel 8-bit 0.7-GS/s A/D converter implemented in a 65-nm CMOS process. The required thresholds are generated from the resistive interpolation embedded within the preamplifier preceding the latches. The active area of the chip is 150 × 220 μm2 and the total power consumption is 5.96 mW. At Nyquist, the ADC achieves 6.62 ENOB, resulting in a figure of merit equal to 86.7 fJ/conversion-step.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
