低功耗的最佳电压和尺寸[CMOS VLSI]

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013) Pub Date : 1999-01-07 DOI:10.1109/ICVD.1999.745193

M. Stan

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引用次数: 39

摘要

我们为选择最佳电源和阈值电压以及最小能量延迟产品的尺寸提供了分析性的“信封背面”计算。基于这样的计算，我们随后表明，在存在互连寄生的情况下，具有单独逻辑和缓冲级的电路设计风格提供了更好的能量延迟产品。

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Optimal voltages and sizing for low power [CMOS VLSI]

We provide analytical "back of the envelope" calculations for the choice of optimal supply and threshold voltages and sizing for minimum energy-delay product. Based on such calculations we then show that a circuit design style with separate logic and buffer stages offers a better energy-delay product in the presence of interconnect parasitics.

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来源期刊

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)

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