Integrated hardware and software for improved flatness measurement: ATC4.1 flip chip assembly case studies

Over the past four decades, electronic packaging technology has evolved from peripheral, through-hole, and bulk configurations to area-array. surface-mount, and small-profile approaches. Among these approaches, flip chip attachment has become the favorable choice for its capability of high volume of input/output and short path of signal distribution. Given the projection that the chip size and power of a single chip package will increase dramatically. substrate warpage of flip-chip packages during assembly and usage has become one of the main concerns. Warpage could cause misalignment between the chip and the substrate, prevent the solder balls from making contact with the substrate flip chip pads during the reflow soldering process, or induce crack nucleation at the board underfill interface in long-term usage. In this research, the authors developed an integrated shadow moire system for improved warpage analysis. The hardware is designed to carry out warpage measurement with a resolution on the order of microns. Combined with software, the integrated system is fully automated and highly accurate. As case studies, the system is used to characterize the substrate warpage of flip chip on organic board assemblies. Warpage of the substrates at the initial bare-board stage, post-reflow, and post-underfill are measured at room temperature. It is found that by properly selecting initially warped substrates, warpage can be diminished during the assembly processes. In addition, warpage measurements at elevated temperatures during thermal cycling and power cycling show that power cycling poses a smaller impact on substrate warpage.