{"title":"快速，密集，可预测和100%可路由的MACH 3和4系列","authors":"O. Agrawal","doi":"10.1109/WESCON.1994.403525","DOIUrl":null,"url":null,"abstract":"This paper focuses on the silicon architecture of AMD's second generation Macro Array CMOS High Speed/High Density (MACH) family of PLDs. Implemented with an advanced 0.65 /spl mu/m technology and driven strongly by customer needs MACH 3 and 4 family is optimized for speed, predictability, density, flexibility and 100% routability. The major thrusts for the family are to allow the following: design changes without changing pinouts, 100% routability. Flexible PAL blocks, synchronous/asynchronous flexible macrocells with built-in XOR capability and up to 20 product terms of logic without any incremental delay, flexible set/reset and clocking control and 5 V in-circuit programmability with IEEE 1149.1 JTAG interface in 100-208 pins PQFP packages. MACH 3 and 4 family is designed to offer fixed, predictable worst-case pin-to-pin delays of 15 ns and external systems clock frequency up to 50+ MHz.<<ETX>>","PeriodicalId":136567,"journal":{"name":"Proceedings of WESCON '94","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Fast, dense, predictable and 100% routable MACH 3 and 4 family\",\"authors\":\"O. Agrawal\",\"doi\":\"10.1109/WESCON.1994.403525\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper focuses on the silicon architecture of AMD's second generation Macro Array CMOS High Speed/High Density (MACH) family of PLDs. Implemented with an advanced 0.65 /spl mu/m technology and driven strongly by customer needs MACH 3 and 4 family is optimized for speed, predictability, density, flexibility and 100% routability. The major thrusts for the family are to allow the following: design changes without changing pinouts, 100% routability. Flexible PAL blocks, synchronous/asynchronous flexible macrocells with built-in XOR capability and up to 20 product terms of logic without any incremental delay, flexible set/reset and clocking control and 5 V in-circuit programmability with IEEE 1149.1 JTAG interface in 100-208 pins PQFP packages. MACH 3 and 4 family is designed to offer fixed, predictable worst-case pin-to-pin delays of 15 ns and external systems clock frequency up to 50+ MHz.<<ETX>>\",\"PeriodicalId\":136567,\"journal\":{\"name\":\"Proceedings of WESCON '94\",\"volume\":\"18 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-09-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of WESCON '94\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/WESCON.1994.403525\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of WESCON '94","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/WESCON.1994.403525","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Fast, dense, predictable and 100% routable MACH 3 and 4 family
This paper focuses on the silicon architecture of AMD's second generation Macro Array CMOS High Speed/High Density (MACH) family of PLDs. Implemented with an advanced 0.65 /spl mu/m technology and driven strongly by customer needs MACH 3 and 4 family is optimized for speed, predictability, density, flexibility and 100% routability. The major thrusts for the family are to allow the following: design changes without changing pinouts, 100% routability. Flexible PAL blocks, synchronous/asynchronous flexible macrocells with built-in XOR capability and up to 20 product terms of logic without any incremental delay, flexible set/reset and clocking control and 5 V in-circuit programmability with IEEE 1149.1 JTAG interface in 100-208 pins PQFP packages. MACH 3 and 4 family is designed to offer fixed, predictable worst-case pin-to-pin delays of 15 ns and external systems clock frequency up to 50+ MHz.<>
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