一个45ns 16×16 CMOS乘法器

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1984.1156616

Y. Kaji, N. Sugiyama, Y. Kitamura, S. Ohya, M. Kikuchi

{"title":"一个45ns 16×16 CMOS乘法器","authors":"Y. Kaji, N. Sugiyama, Y. Kitamura, S. Ohya, M. Kikuchi","doi":"10.1109/ISSCC.1984.1156616","DOIUrl":null,"url":null,"abstract":"A 16 × 16 parallel multiplier, using 1.5μm design rule N-well CMOS technology, will be covered. A multiply time of 45ns has been achieved by using Booth's algorithm and Wallace tree reduction. The typical power dissipation is 100mW.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"73 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"A 45ns 16×16 CMOS multiplier\",\"authors\":\"Y. Kaji, N. Sugiyama, Y. Kitamura, S. Ohya, M. Kikuchi\",\"doi\":\"10.1109/ISSCC.1984.1156616\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 16 × 16 parallel multiplier, using 1.5μm design rule N-well CMOS technology, will be covered. A multiply time of 45ns has been achieved by using Booth's algorithm and Wallace tree reduction. The typical power dissipation is 100mW.\",\"PeriodicalId\":260117,\"journal\":{\"name\":\"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"volume\":\"73 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.1984.1156616\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1984.1156616","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 6

摘要

介绍了一种采用1.5μm设计规则n阱CMOS技术的16 × 16并行乘法器。利用Booth算法和Wallace树约简实现了45ns的乘法时间。典型功耗为100mW。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

A 45ns 16×16 CMOS multiplier

A 16 × 16 parallel multiplier, using 1.5μm design rule N-well CMOS technology, will be covered. A multiply time of 45ns has been achieved by using Booth's algorithm and Wallace tree reduction. The typical power dissipation is 100mW.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

自引率

0.00%

发文量