Notice of Violation of IEEE Publication PrinciplesA 10GHz Low Phase Noise 0.13μm CMOS LC-VCO for Mixed Signal SoCs Using Noise Rejection Caged Inductors

Several coupled noise rejection techniques are proposed for LC oscillators operating in noisy mixed signal SoC environment. A simple metal guard ring around the LC-VCO can achieve up to lOdB of coupled noise rejection with a minimal area penalty and no additional processing steps. The best noise rejection (>60dB) was achieved with a full metal cage realized both in IC metal layers and in thick package layers. A compromise between cost, area and performance was achieved with a partial metal cage with no top plate and having graded lateral walls and a grid type bottom plate halo. Spur rejection up to 35 dB with only a 10% penalty in inductor quality factor were achieved. The different inductor structures were realized in 0.13 mum CMOS and the phase noise and spur rejection capability were investigated while operating on the same die with a large digital core.