Peter Caputa, M. Anders, C. Svensson, R. Krishnamurthy, S. Borkar
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A low-swing single-ended L1 cache bus technique for sub-90nm technologies
This paper describes a 3.3 GHz low-swing single-ended L1 cache bus in 1.2 V, 90 nm dual-Vt CMOS technology. Accurate RLCK-modeling of the interconnect topology has been conducted using a 3D field solver. A signal-swing reduction of 25% and efficient sense amplifier-based receiver are employed to reach 3.3 GHz, 2.24 mW operation at 1.2 V and 110/spl deg/C. 70% energy and 54% peak-current reduction is achieved over an optimized high-performance conventional dynamic cache bus scheme. The design is fully functional up to 6.1 GHz operating-frequency with a 54% eye opening.
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