Highly Linear 4-bit Flash ADC Implemented in 22 nm FD-SOI Process

This paper presents the design of 4-bit flash type analog-to-digital converter implemented in 22 nm FD-SOI technology with 0.8 V supply voltage. This block is part of original sub-ranging ADC whose working principle is based on the assumption that sub-ADC and sub-DAC exhibit high linearity while they nominal resolutions remain relatively low. The linearity of the presented flash ADC has to be as high as in case of 8-bit converter. Thus, the most challenging task was to design comparator with resolution of ±1.5 mV. This goal was reached owing to ability offered by the FD-SOI process to trim transistor’s threshold voltage by means of modulating the back-gate polarization. The resulting sampling rate is 500 Ms/s.