The STG DICE Cell with the Decoder for Reading Data in Steady and Unsteady States for Hardened SRAM

The new design technique is proposed for memory elements, which are not sensitive to induced single upsets. This is the STG DICE cell with the new scheme of the decoder for reading data in steady and unsteady states of the cell’s nodes. The topology of the STG DICE cell (Spaced Transistor Groups DICE) is different from the standard DICE in that the transistors are devided into two groups so that the impact of single nuclear particles on one group does not lead to upset of this cell. The 65 nm CMOS DICE with the new scheme of the decoder for reading data was simulated using TCAD methodology. The decoder consists of two tristate inverters and two normal inverters. In combinational logic of the decoder can be short-term noise pulses in the range of the linear energy transfer of single particles on the tracks of 20–80 MeV $\times $ cm2/mg.