{"title":"基于垂直纳米线晶体管的CMOS: VTC分析","authors":"S. Maheshwaram, S. Manhas, B. Anand","doi":"10.1109/ICEMELEC.2014.7151187","DOIUrl":null,"url":null,"abstract":"In this paper, a detailed analysis of the voltage transfer characteristics of vertical nanowire transistor-based CMOS inverter is presented. We show that noise margins are strongly dependent on the source/drain series resistance, and that the extension lengths can be used as tuning parameters to control the noise margin and gains of the inverter.","PeriodicalId":186054,"journal":{"name":"2014 IEEE 2nd International Conference on Emerging Electronics (ICEE)","volume":"121 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Vertical nanowire transistor-based CMOS: VTC analysis\",\"authors\":\"S. Maheshwaram, S. Manhas, B. Anand\",\"doi\":\"10.1109/ICEMELEC.2014.7151187\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, a detailed analysis of the voltage transfer characteristics of vertical nanowire transistor-based CMOS inverter is presented. We show that noise margins are strongly dependent on the source/drain series resistance, and that the extension lengths can be used as tuning parameters to control the noise margin and gains of the inverter.\",\"PeriodicalId\":186054,\"journal\":{\"name\":\"2014 IEEE 2nd International Conference on Emerging Electronics (ICEE)\",\"volume\":\"121 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 IEEE 2nd International Conference on Emerging Electronics (ICEE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICEMELEC.2014.7151187\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 IEEE 2nd International Conference on Emerging Electronics (ICEE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICEMELEC.2014.7151187","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
In this paper, a detailed analysis of the voltage transfer characteristics of vertical nanowire transistor-based CMOS inverter is presented. We show that noise margins are strongly dependent on the source/drain series resistance, and that the extension lengths can be used as tuning parameters to control the noise margin and gains of the inverter.