{"title":"新型开关数少的多电平逆变器仿真分析","authors":"K. Dhivakar, V. Thiyagarajan","doi":"10.1109/ICEES.2018.8443205","DOIUrl":null,"url":null,"abstract":"In this paper, a inverter topology with reduced number of switches has been proposed. The proposed topology uses six switches and 4 voltage sources. The output voltage of the inverter is a smooth stepped waveform. The number of levels in the waveform depends upon the number of voltage sources and the power electronic switches. There are two configurations in multilevel inverter, namely symmetrical and asymmetrical configuration. The proposed inverter can operate in both symmetric and asymmetrical configuration. In symmetrical configuration 5-level output waveform is achieved while in asymmetrical configuration 7-level output is achieved. Several switching strategies have been adopted to minimize the total harmonic distortion (THD) of the output waveform. The working and performance of the proposed topology is tested with the help of MATLAB software.","PeriodicalId":134828,"journal":{"name":"2018 4th International Conference on Electrical Energy Systems (ICEES)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Simulation Analysis of New Multilevel Inverter with Reduced Number of Switches\",\"authors\":\"K. Dhivakar, V. Thiyagarajan\",\"doi\":\"10.1109/ICEES.2018.8443205\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, a inverter topology with reduced number of switches has been proposed. The proposed topology uses six switches and 4 voltage sources. The output voltage of the inverter is a smooth stepped waveform. The number of levels in the waveform depends upon the number of voltage sources and the power electronic switches. There are two configurations in multilevel inverter, namely symmetrical and asymmetrical configuration. The proposed inverter can operate in both symmetric and asymmetrical configuration. In symmetrical configuration 5-level output waveform is achieved while in asymmetrical configuration 7-level output is achieved. Several switching strategies have been adopted to minimize the total harmonic distortion (THD) of the output waveform. The working and performance of the proposed topology is tested with the help of MATLAB software.\",\"PeriodicalId\":134828,\"journal\":{\"name\":\"2018 4th International Conference on Electrical Energy Systems (ICEES)\",\"volume\":\"51 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-02-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 4th International Conference on Electrical Energy Systems (ICEES)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICEES.2018.8443205\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 4th International Conference on Electrical Energy Systems (ICEES)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICEES.2018.8443205","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Simulation Analysis of New Multilevel Inverter with Reduced Number of Switches
In this paper, a inverter topology with reduced number of switches has been proposed. The proposed topology uses six switches and 4 voltage sources. The output voltage of the inverter is a smooth stepped waveform. The number of levels in the waveform depends upon the number of voltage sources and the power electronic switches. There are two configurations in multilevel inverter, namely symmetrical and asymmetrical configuration. The proposed inverter can operate in both symmetric and asymmetrical configuration. In symmetrical configuration 5-level output waveform is achieved while in asymmetrical configuration 7-level output is achieved. Several switching strategies have been adopted to minimize the total harmonic distortion (THD) of the output waveform. The working and performance of the proposed topology is tested with the help of MATLAB software.
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