电阻负载sram的偶然性SEU硬化

Proceedings of the Third European Conference on Radiation and its Effects on Components and Systems Pub Date : 1995-09-18 DOI:10.1109/RADECS.1995.509802

R. Koga, J. Kirshman, S. D. Pinkerton, S. Hansel, K. Crawford, W. Crain

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引用次数: 2

摘要

对美光科技的MT5C1008C(128 K/spl次/8)和MT5C2561C(256 K/spl次/1)高电阻和低电阻负载版本的sram进行了SEU漏洞测试。低阻载sram的误码率为“1”/spl rarr/“0”和“0”/spl rarr/“1”，误码率接近于1;相反，高阻负载器件表现出明显的误差位极性效应。提出了两种不同的扰动机制来解释这些观察结果。

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Serendipitous SEU hardening of resistive load SRAMs

High and low resistive load versions of Micron Technology's MT5C1008C(128 K/spl times/8) and MT5C2561C(256 K/spl times/1) SRAMs were tested for SEU vulnerability. Contrary to computer simulation results, SEU susceptibility decreased with increasing resistive load A substantially larger number of multiple-bit errors were observed for the low resistive load SRAMs, which also exhibited a "1"/spl rarr/"0" to "0"/spl rarr/"1" bit error ratio close to unity; in contrast, the high resistive load devices displayed a pronounced error bit polarity effect. Two distinct upset mechanisms are proposed to account for these observations.

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Proceedings of the Third European Conference on Radiation and its Effects on Components and Systems

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