基于VIO的32位ALU的设计、实现与验证

D. A. Devi, L. Sugun
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引用次数: 8

摘要

任何数字设计都可以通过使用VHDL或Verilog_HDL表示为RTL形式。这样的设计可以通过流行的前端工具Xilinx和FPGA开发板进行仿真、合成、实现,最后可以进行验证。在这种情况下,如果设计规范足够大,难以在目标板上验证功能,那么我们可以使用虚拟I/O概念。虚拟输入/输出(VIO)调试功能可以实时监控和驱动FPGA内部信号。当不可能访问目标硬件上的物理输入和输出设备时使用此功能,我们可以使用此调试功能来驱动和监视实际硬件上存在的信号。本文设计了一个32位ALU,并通过VIO进行了仿真和验证。本工作采用Verilog HDL进行设计,使用Xilinx Vivado System Design Suite 2017.1和Nexys DDR4 FPGA开发板实现。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Design, implementation and verification of 32-Bit ALU with VIO
Any Digital design can be represented as RTL form by using either VHDL or Verilog_HDL. Such designs can be simulated, synthesized, implemented and finally can be verified by using popular front end tool Xilinx and FPGA development boards. In such cases, if the design specification is large enough to face the difficulty to verify the functionality on the target board, then we can use the virtual I/O concept. The Virtual Input/Output (VIO) debug feature can both monitor and drive internal FPGA signals in real time. This feature is used when there is no possibility to access on physical input and output devices on the target hardware, we can use this debug feature to drive and monitor signals that are present on the real hardware. In the proposed work a 32-bit ALU is designed simulated and verified through VIO. This work is designed with Verilog HDL, and implemented with Xilinx Vivado System Design Suite 2017.1 and Nexys DDR4 FPGA development board is used.
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