A high performance Rad hard 2-3 GHz integer N CMOS phase lock loop

We report here on the performance of a 2-3 GHz Phase Lock Loop (PLL) designed specifically for commercial space applications requiring low power dissipation, very good phase noise, good temperature stability, excellent SEE tolerance, and little degradation over a 100 kRad(Si) total dose exposure. The device is built in a 0.5 /spl mu/m fully depleted ultra thin silicon on sapphire technology (UTSi). Product level radiation data is presented showing performance as a function of total dose. Following gamma exposures to 100 kRad(Si), the device shows an integrated phase noise of less than 0.8 degree for 2.18 GHz operation for frequency step sizes of 1 MHz. This is a performance level exceeding all known integrated PLL's currently in the commercial marketplace.