Achieving high-performance Ge MOS devices using high-к gate dielectrics Ga2O3(Gd2O3) of sub-nm EOT

When channel materials other than Si are being considered to enhance the carrier mobility, Ge has always been one viable candidate since it possesses higher carrier mobility than those of Si. However, it is difficult to achieve a high-quality oxide/Ge interface comparable to SiO2/Si due to unfavorable surface properties and water-soluble native oxides of Ge. Over the past 4–5 years, two major techniques have been shown to effectively passivate the Ge surface by utilizing Si(SiO2) [1] and thermally grown stoichiometric GeO2 [2,3] as the passivation layers, thus giving low Dit's of ∼10¹¹ cm⁻²eV⁻¹. However, the use of the interfacial passivation layers (IPL) encountered a major hindrance primarily due to their relatively lower к values which have an adverse effect on the critical requirement of great reduction of equivalent oxide thickness (EOT) for future CMOS applications. An effective approach to achieve the ultimate EOT down-scaling is to directly deposit high-к dielectrics on Ge without IPLs, while maintaining a high к value and decent oxide/Ge interface quality.