S. Drago, D. Leenaerts, B. Nauta, F. Sebastiano, K. Makinwa, L. Breems
{"title":"用于无线传感器节点的200µA占空环锁相环","authors":"S. Drago, D. Leenaerts, B. Nauta, F. Sebastiano, K. Makinwa, L. Breems","doi":"10.1109/ESSCIRC.2009.5325979","DOIUrl":null,"url":null,"abstract":"A duty-cycled PLL operating in burst mode is presented. It is an essential building block of a moderately accurate low-power frequency synthesizer suitable for use in nodes for Wireless Sensor Networks. Once in lock, the PLL's frequency error is less than 0.1% (rms). Fabricated in a baseline 65 nm CMOS process, the PLL occupies 0.19X0.15 mm2 and draws 200 µA from a 1.3-V supply when generating a 1 GHz signal with a duty cycle of 10%.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-09-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A 200 µA duty-cycled PLL for wireless sensor nodes\",\"authors\":\"S. Drago, D. Leenaerts, B. Nauta, F. Sebastiano, K. Makinwa, L. Breems\",\"doi\":\"10.1109/ESSCIRC.2009.5325979\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A duty-cycled PLL operating in burst mode is presented. It is an essential building block of a moderately accurate low-power frequency synthesizer suitable for use in nodes for Wireless Sensor Networks. Once in lock, the PLL's frequency error is less than 0.1% (rms). Fabricated in a baseline 65 nm CMOS process, the PLL occupies 0.19X0.15 mm2 and draws 200 µA from a 1.3-V supply when generating a 1 GHz signal with a duty cycle of 10%.\",\"PeriodicalId\":258889,\"journal\":{\"name\":\"2009 Proceedings of ESSCIRC\",\"volume\":\"10 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-09-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 Proceedings of ESSCIRC\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.2009.5325979\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 Proceedings of ESSCIRC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2009.5325979","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 200 µA duty-cycled PLL for wireless sensor nodes
A duty-cycled PLL operating in burst mode is presented. It is an essential building block of a moderately accurate low-power frequency synthesizer suitable for use in nodes for Wireless Sensor Networks. Once in lock, the PLL's frequency error is less than 0.1% (rms). Fabricated in a baseline 65 nm CMOS process, the PLL occupies 0.19X0.15 mm2 and draws 200 µA from a 1.3-V supply when generating a 1 GHz signal with a duty cycle of 10%.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
