一种新型7gbps低功耗CMOS超宽带脉冲发生器

M. A. Arafat, A. Rashid
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引用次数: 10

摘要

本研究提出一种新颖的低功耗高数据速率超宽带脉冲产生电路,可完全集成于互补金属氧化物半导体(CMOS)工艺中。该电路的基本部分采用三角脉冲产生技术产生超宽带高斯单周期脉冲。设计了一种新型双极相移键控脉冲调制器,用于控制输出脉冲的极性。该设计包括附加功能,使脉冲发生器也适用于传输参考(TR)信号系统。该电路在无TRP脉冲和有TRP脉冲时的最大脉冲速率分别为7gpps和3.5 Gpps。产生的脉冲是对称的,每个脉冲的宽度为142 ps,峰对峰摆幅为500 mV。脉冲频谱−3db带宽为9ghz。脉冲发生器从1.2 V电源中每脉冲仅消耗1.13 pJ。采用90nm CMOS工艺设计并仿真了该电路。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A novel 7 Gbps low-power CMOS ultra-wideband pulse generator
In this study, a novel low-power high data rate ultra-wideband (UWB) pulse generator circuit is presented, which can be fully integrated in complementary metal oxide semiconductor (CMOS) process. The basic part of the circuit generates a UWB Gaussian monocycle pulse using the triangular pulse generation technique. A new bipolar phase shift keying pulse modulator is designed to control the polarity of the output pulses. The design includes additional functionality to make the pulse generator also applicable for transmitted reference (TR) signalling system. The circuit can generate pulses at a maximum rate of 7 giga pulse per second (Gpps) without TR pulse (TRP) and 3.5 Gpps with TRP. The generated pulses are symmetrical, each having a width of 142 ps and a peak-to-peak swing of 500 mV. The −3 dB bandwidth of the pulse spectrum is 9 GHz. The pulse generator consumes only 1.13 pJ per pulse from 1.2 V supply. The circuit is designed and simulated in 90 nm CMOS technology.
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