Comprehensive 3D TSV Reliability Study on 14nm FINFET Technology with Thinned Wafers

The impact of wafer level reliability of TSV has been studied with respect to FEOL (Front End of Line) and BEOL (Back End of Line) reliability. A TSV keep out zone (KOZ) study has been done with varying gate length and width of transistor. Gate voltage (Vg) vs saturation current (Idsat) behavior indicates that there is negligible impact on Idsat due to mechanical stress of the TSV for 5 μ m} KOZ for both NFET and PFET devices fabricated with thin and thick gate-oxide dielectric. Voltage Ramp Stress (VRS) and Constant Voltage Stress (CVS) tests were performed at 25°C and 125°C to study the FEOL gate dielectric and device reliability such as gate dielectric breakdown voltage (VBD), Hot Carrier Injection (HCI), and Bias Temperature Instability (BTI). Apart from FEOL reliability study, special test structures were also designed to capture even a minor TSV impact on the lower metal and via levels of the BEOL stack. Time Dependent Dielectric Breakdown (TDDB), Electro migration (EM), and Stress Migration (SM) were performed to investigate any potential impact to BEOL due to TSV mechanical stress or Cu pumping effects. TSV KOZ impact on electrostatic discharge (ESD) protection devices was also performed. Our study with thick and thin TSV wafer showed no significant impact of TSV integration approach on FEOL, BEOL and ESD reliability.