E. Chen, D. Lottis, A. Driskill-Smith, D. Druist, V. Nikitin, S. Watts, Xueti Tang, D. Apalkov
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Non-volatile STT-RAM (spin transfer torque random access memory) is a new memory technology that combines the capacity and cost benefits of DRAM, the fast read and write performance of SRAM and the non-volatility of Flash with essentially unlimited endurance. It has excellent write selectivity, excellent scalability beyond the 45 nm technology node, low power consumption, and a simpler architecture and manufacturing process than first-generation, field-switched MRAM. A magnetic tunnel junction (MTJ) device (Fig. 1) is used as the information storage memory element, and its magneto-resistance is used for information read-out. To make the STT-RAM technology competitive with mainstream semiconductor memories, the writing current has to be reduced so that the MTJ can be switched by a minimum sized CMOS transistor. In this paper, we discuss our approaches and results in writing current reduction; device read and write performances; robustness against read disturb switching and barrier break down; and prospects of scaling to future smaller nodes.