用CADENCE实现CMOS模拟模块的布局自动化

[Proceedings] EURO ASIC `90 Pub Date : 1990-05-29 DOI:10.1109/EASIC.1990.207915

D. Dzahini, F. Gaffiot, B. Boutherin, M. Le Helley

{"title":"用CADENCE实现CMOS模拟模块的布局自动化","authors":"D. Dzahini, F. Gaffiot, B. Boutherin, M. Le Helley","doi":"10.1109/EASIC.1990.207915","DOIUrl":null,"url":null,"abstract":"Presents a set of tools for aiding to the design of analog CMOS circuits. The procedures described can generate automatically the layout of CMOS cells. In addition to the electrical parameters of each component, transistor, resistors, capacitors, the designer can give a shape description which will be used for placement and routing. The layout is generated with respect to specified design rules. The procedures have been written in SKILL language. SKILL is a trademark of CADENCE.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Layout automation of CMOS analog building blocks with CADENCE\",\"authors\":\"D. Dzahini, F. Gaffiot, B. Boutherin, M. Le Helley\",\"doi\":\"10.1109/EASIC.1990.207915\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Presents a set of tools for aiding to the design of analog CMOS circuits. The procedures described can generate automatically the layout of CMOS cells. In addition to the electrical parameters of each component, transistor, resistors, capacitors, the designer can give a shape description which will be used for placement and routing. The layout is generated with respect to specified design rules. The procedures have been written in SKILL language. SKILL is a trademark of CADENCE.<<ETX>>\",\"PeriodicalId\":205695,\"journal\":{\"name\":\"[Proceedings] EURO ASIC `90\",\"volume\":\"18 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-05-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[Proceedings] EURO ASIC `90\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EASIC.1990.207915\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[Proceedings] EURO ASIC `90","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EASIC.1990.207915","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 5

摘要

提出了一套辅助设计模拟CMOS电路的工具。所描述的程序可以自动生成CMOS单元的布局。除了每个元件、晶体管、电阻器、电容器的电气参数外，设计人员还可以给出用于放置和布线的形状描述。布局是根据指定的设计规则生成的。程序是用SKILL语言编写的。SKILL是CADENCE的商标。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Layout automation of CMOS analog building blocks with CADENCE

Presents a set of tools for aiding to the design of analog CMOS circuits. The procedures described can generate automatically the layout of CMOS cells. In addition to the electrical parameters of each component, transistor, resistors, capacitors, the designer can give a shape description which will be used for placement and routing. The layout is generated with respect to specified design rules. The procedures have been written in SKILL language. SKILL is a trademark of CADENCE.<>

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

[Proceedings] EURO ASIC `90

自引率

0.00%

发文量