用于16mb及以上ram的多晶硅tft的发展

51st Annual Device Research Conference Pub Date : 1993-06-21 DOI:10.1109/DRC.1993.1009597

S. Batra, R. Maddox, L. Tran, M. Manning, C. Dennison, P. Fazan

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引用次数: 4

摘要

只提供摘要形式。作者讨论了薄膜晶体管(TFTs)的多晶硅颗粒微观结构、栅极介电和掺光漏极偏置(LDO)的发展和优化。本研究中使用的标称tft的W/L为0.7/1.2 μ m，漏极偏移量为0.3 μ m。评估了厚度为10-50 nm的不同栅极电介质(SiO/sub 2/， NO, ONO)。结果表明，LDO植入物对于获得大于10/sup /的开/关比，同时降低TFT对漏极偏置失调的灵敏度至关重要。ONO电介质在氧化物泄漏和开/关比方面优于NO堆叠或氧化物。固相结晶(SPC)后注入3*10/sup 14/ Si，通过降低界面陷阱密度提高了斜率。因此，使用具有堆叠栅极的LDO tft和SPC后的Si植入物可以实现泄漏(10/sup 6/)的显着性能增强。>

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Development of polysilicon TFTs for 16 MB SRAMs and beyond

Summary form only given. The authors discuss the development and optimization of polysilicon grain microstructure, gate dielectric ,and light doped drain offset (LDO) for thin-film transistors (TFTs). The nominal TFTs used in this study had a W/L of 0.7/1.2 mu m with a drain offset of 0.3 mu m. Different gate dielectrics (SiO/sub 2/, NO, ONO) with thickness of 10-50 nm were evaluated. The results suggest that an LDO implant is essential for obtaining ON/OFF ratios greater than 10/sup 5/ while reducing the TFT sensitivity to drain-offset misalignment. The ONO dielectric is superior to NO stacks or oxide in terms of oxide leakage and ON/OFF ratios. A 3*10/sup 14/ Si implant after solid-phase crystallization (SPC) improves the slope by reducing the interface trap density. Therefore, significant performance enhancements in leakage ( 10/sup 6/) can be realized using LDO TFTs with stacked gates and an Si implant following SPC. >

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51st Annual Device Research Conference

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