Wu Jianping, Yu-tang Ye, Liu Lin, Huang Bingquan, Guo Tao
{"title":"基于高速fpga的SOPC货币分拣系统应用","authors":"Wu Jianping, Yu-tang Ye, Liu Lin, Huang Bingquan, Guo Tao","doi":"10.1109/ICEMI.2011.6037771","DOIUrl":null,"url":null,"abstract":"A high-speed real-time currency sorting system based on SOPC of FPGA is designed against the existing problems in our country, such as the high complexity, the lower stability, the low real-time performance of complex algorithms for high-speed digital image signal and that the system is difficult to upgrade in real time, etc. The methods of software simulation, real-time debugging online are applied; the real-time processing of complex image algorithms has been achieved successfully and the system complexity has been reduced; the integration and stability of the system have been greatly improved. Furthermore the operation of FPGA could be performed in parallel and the responsive time of its hardware could be accurate to nanosecond (ns) level. So the real-time processing properties of the system have more advantages against other processing platforms. Because of the system programmable performance, the real-time updates of the system without changing the hardware circuit have also been implemented.","PeriodicalId":321964,"journal":{"name":"IEEE 2011 10th International Conference on Electronic Measurement & Instruments","volume":"2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"High-speed FPGA-based SOPC application for currency sorting system\",\"authors\":\"Wu Jianping, Yu-tang Ye, Liu Lin, Huang Bingquan, Guo Tao\",\"doi\":\"10.1109/ICEMI.2011.6037771\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A high-speed real-time currency sorting system based on SOPC of FPGA is designed against the existing problems in our country, such as the high complexity, the lower stability, the low real-time performance of complex algorithms for high-speed digital image signal and that the system is difficult to upgrade in real time, etc. The methods of software simulation, real-time debugging online are applied; the real-time processing of complex image algorithms has been achieved successfully and the system complexity has been reduced; the integration and stability of the system have been greatly improved. Furthermore the operation of FPGA could be performed in parallel and the responsive time of its hardware could be accurate to nanosecond (ns) level. So the real-time processing properties of the system have more advantages against other processing platforms. Because of the system programmable performance, the real-time updates of the system without changing the hardware circuit have also been implemented.\",\"PeriodicalId\":321964,\"journal\":{\"name\":\"IEEE 2011 10th International Conference on Electronic Measurement & Instruments\",\"volume\":\"2 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-10-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE 2011 10th International Conference on Electronic Measurement & Instruments\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICEMI.2011.6037771\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE 2011 10th International Conference on Electronic Measurement & Instruments","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICEMI.2011.6037771","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
High-speed FPGA-based SOPC application for currency sorting system
A high-speed real-time currency sorting system based on SOPC of FPGA is designed against the existing problems in our country, such as the high complexity, the lower stability, the low real-time performance of complex algorithms for high-speed digital image signal and that the system is difficult to upgrade in real time, etc. The methods of software simulation, real-time debugging online are applied; the real-time processing of complex image algorithms has been achieved successfully and the system complexity has been reduced; the integration and stability of the system have been greatly improved. Furthermore the operation of FPGA could be performed in parallel and the responsive time of its hardware could be accurate to nanosecond (ns) level. So the real-time processing properties of the system have more advantages against other processing platforms. Because of the system programmable performance, the real-time updates of the system without changing the hardware circuit have also been implemented.