Thermal effects in 3D sequential technology

We present for the first time an experimental study of thermal effects in 3D sequential integration, including Self-Heating Effect (SHE) and thermal coupling between the two levels of ultra-thin body FDSOI transistors. We extracted a large set of experimental data using different thermometry techniques, and different heater-sensor configurations allowed by this specific stacked integration. We described SHE in top and bottom transistor levels, as well as the influence of a transistor in ON state on a transistor stacked above or below. At the same time, we provide for the first time an experimental validation that the temperature increase given by gate resistance thermometry technique is equal to the temperature in the channel given by the subthreshold slope. Finally, this work can be also used to manage thermal effects for logic or analog applications, and help further optimization of 3D sequential integrated circuits through both technology and design solutions.