Implications of voltage and dimension scaling on CMOS testing: the multidimensional testing paradigm

Recent developments and future trends in VLSI/ULSI process and design technologies are introducing new levels of complexity in testing. This paper explains why modern submicron CMOS technologies are stretching test capabilities, making it easier for failures in digital integrated circuits (ICs) to elude test. Submicron transistor technologies are being forced to shift to lower power-supply voltages to maintain the internal electric field in the MOS transistors, and also to reduce power consumption. The consequent reduction of threshold voltage and the increase of leakage current are decreasing the effectiveness of quiescent control monitoring (I/sub DDQ/) testing because the reduced ratio between the MOSFET's on and of currents is making this testing technique impracticable. A possible solution to fault test escape is presented in terms of a new testing methodology: the Multidimensional Testing Paradigm (MTP). This methodology is based on the use of voltage, temperature, and frequency parameterized testing. The impact of device dimension scaling on submicron CMOS digital circuits is illustrated. Bridging faults (BFs), faults causing two physically adjacent node, in the layout of a circuit to be electrically connected to each other, are used as a representative class of fault model, and their effect on the electrical behavior of a simple digital system are described. The traditional analysis of a static gate properties as a function of the short's resistances, based on the use of the gate logic threshold as a pivot, is demonstrated to be inadequate for modern microelectronic technologies. A new, more meaningful classification of BF resistance values is introduced.