HDL implementation of digital filters using floating point vedic multiplier

Multiplication is one of the important operations in many signal processing applications such as digital filters design, fast Fourier transform (FFT), discrete Fourier transform (DFT), discrete cosine transform (DCT), etc. The performance of multiplier has direct effect on the final output of those applications. Due to this, there is always a need to design a multiplier which has high accuracy with high speed and low power consumption. Moreover, it is also desirable to have multiplier with less area and complexity. In this paper, we address the problem of hardware description language (HDL) implementation of digital filters using vedic multiplier with Urdhva-Triyakbhyam sutra. Vedic multiplication is used in finite impulse response (FIR) and infinite impulse response (IIR) filters as a basic building block with single precision floating point format which increases the accuracy and range of multiplication coefficients. The potential of the proposed algorithm is evaluated by comparing its performance with other existing multipliers such as shift & add, array, and Wallace multipliers. The experimental results show an improvement in terms of area and complexity using the proposed algorithm when compared to the other existing multiplication methods.