加法器卷积神经网络加速器的VLSI架构设计

Mingyong Zhuang, Xinhui Liao, Huhong Wu, Jianyang Zhou, Zichao Guo
{"title":"加法器卷积神经网络加速器的VLSI架构设计","authors":"Mingyong Zhuang, Xinhui Liao, Huhong Wu, Jianyang Zhou, Zichao Guo","doi":"10.1109/asid52932.2021.9651682","DOIUrl":null,"url":null,"abstract":"Convolution Neural Network (ConvNet) achieved good performance in a variety of image processing tasks. How-ever, a large number of multiplication operations in convolution layers affect mobile device deployment of the ConvNet. Recently, an Adder Convolution Network (AdderNet) was proposed to reduce the multiplication operations of common convolutional neural networks. In this paper, we analyzed differences in calculation processes between the AdderNet and the ConvNet and proposed the VLSI architecture of the AdderNet. In addition to analyzing resource consumption of adder convolutional layers, we also built the whole LeNet neural network with the adder convolutional layers and calculated inference latency. Experiment results showed the proposed VLSI architecture of the AdderNet reduced the latency by 29.26%. Compared with the multiplication convolution layer, the resource consumptions of DSP, Flip-Flop, and LUT for the adder convolution layer were reduced respectively by 6.25%, 0.31%, and 0.86%.","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"VLSI Architecture Design for Adder Convolution Neural Network Accelerator\",\"authors\":\"Mingyong Zhuang, Xinhui Liao, Huhong Wu, Jianyang Zhou, Zichao Guo\",\"doi\":\"10.1109/asid52932.2021.9651682\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Convolution Neural Network (ConvNet) achieved good performance in a variety of image processing tasks. How-ever, a large number of multiplication operations in convolution layers affect mobile device deployment of the ConvNet. Recently, an Adder Convolution Network (AdderNet) was proposed to reduce the multiplication operations of common convolutional neural networks. In this paper, we analyzed differences in calculation processes between the AdderNet and the ConvNet and proposed the VLSI architecture of the AdderNet. In addition to analyzing resource consumption of adder convolutional layers, we also built the whole LeNet neural network with the adder convolutional layers and calculated inference latency. Experiment results showed the proposed VLSI architecture of the AdderNet reduced the latency by 29.26%. Compared with the multiplication convolution layer, the resource consumptions of DSP, Flip-Flop, and LUT for the adder convolution layer were reduced respectively by 6.25%, 0.31%, and 0.86%.\",\"PeriodicalId\":150884,\"journal\":{\"name\":\"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-10-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/asid52932.2021.9651682\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/asid52932.2021.9651682","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3

摘要

卷积神经网络(ConvNet)在各种图像处理任务中取得了良好的性能。然而,卷积层中大量的乘法运算影响了卷积网络在移动设备上的部署。为了减少普通卷积神经网络的乘法运算,最近提出了一种加法器卷积网络(AdderNet)。本文分析了AdderNet和ConvNet在计算过程中的差异,提出了AdderNet的VLSI架构。除了分析加法器卷积层的资源消耗外,我们还用加法器卷积层构建了整个LeNet神经网络,并计算了推理延迟。实验结果表明,AdderNet的VLSI架构将延迟降低了29.26%。与乘法卷积层相比,加法器卷积层对DSP、Flip-Flop和LUT的资源消耗分别降低了6.25%、0.31%和0.86%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
VLSI Architecture Design for Adder Convolution Neural Network Accelerator
Convolution Neural Network (ConvNet) achieved good performance in a variety of image processing tasks. How-ever, a large number of multiplication operations in convolution layers affect mobile device deployment of the ConvNet. Recently, an Adder Convolution Network (AdderNet) was proposed to reduce the multiplication operations of common convolutional neural networks. In this paper, we analyzed differences in calculation processes between the AdderNet and the ConvNet and proposed the VLSI architecture of the AdderNet. In addition to analyzing resource consumption of adder convolutional layers, we also built the whole LeNet neural network with the adder convolutional layers and calculated inference latency. Experiment results showed the proposed VLSI architecture of the AdderNet reduced the latency by 29.26%. Compared with the multiplication convolution layer, the resource consumptions of DSP, Flip-Flop, and LUT for the adder convolution layer were reduced respectively by 6.25%, 0.31%, and 0.86%.
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