LFMAC - Logic encryption of low power full adder with Multiplier and Accumulator as application

In the process of development in the Semiconductor Industry, Intellectual Property (IP) piracy has become a threat to innovation. To reduce this, logic encryption is found to be an effective solution. It is achieved by employing the concept of keys for the circuits. In this paper, logic encryption is a concept is applied to the previously proposed Least Transistor Count (LTC) full adder. The concept of least gates is taken for its advantage for its low power and delay when compared to conventional adders. The proposed work is compared with the LTC full adder and with similar encrypted full adders and has observed 1000 times decrease in power. Delay is recorded as 25ns for sum and 4.32ps for carry signal. The proposed work has 56 per cent more power and 80 per cent more area than the LTC adder. But it has achieved a drop of 59 per cent in transistor count than previous works and a strong level of encryption than previous works. The proposed encrypted full adder is extended to a Multiplier and Accumulator (MAC) unit design. An encrypted MAC design is proposed by focusing on the key combinations and positions.