Investigation on Solder Void Formation Mechanism After High Temperatures Stress by 3D CT Scan and EDX Analysis

In recent years, flip chip packaging by application of a copper pillar bump as an interconnector within the packages has successfully shrunk the package size to a minimum level, by maintaining or maximizing the chip application functionality. Nevertheless, some weaknesses have been observed during the formation of solder joint connection between the copper pillars to die pad substrates. The most common defect, which is solder void formation at the solder joint area, will reduce the interconnection strength or robustness of the solder joint. To understand the solder void formation mechanism, a simulation experiment has been carried out by using copper and silver plated lead pad substrate for pillar solder joint formation process at different stress time interval. An analytical analysis by using 3D CT-scan has been carried out to detect the submicron size solder void defect, especially during high-temperature stress process. An elemental analysis by energy dispersive X-ray also has been carrying out to prove the substrate pad material dissolution mechanism during solder joint formation. With the experiment finding and deeply understanding the material dissolution behavior in packaging concept, this can ensure more robust pillar joint die bond process and guarantee quality packages built.