Efficient sine evaluation architecture for direct digital frequency synthesis

An efficient sine evaluation architecture for direct digital frequency synthesis (DDFS) is presented. The sine values are approximated with the output of a second order interpolator, whose coefficients are stored in a tiny look-up table (LUT). The method allows a strong memory compression ratio, with respect to other approximation solutions, that balances the necessity of two multipliers and two adders. A sine evaluator with 21-b argument and 16-b output has been designed. It is characterized by a maximum absolute error of 0.82 LSB, an output SNR of 97.78 dB and an amplitude contribution to the spectral purity better than 117 dBc. The dimension of the LUT is only 720 b, and the parabolic interpolator has an estimated complexity of about 15,000 transistors. The structure of the evaluator is simple, easily pipelinable, and well suited to an integrated implementation.