混合信号亚微米CMOS集成电路中外延层电阻率效应的评价

2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595) Pub Date : 2002-08-07 DOI:10.1109/MIEL.2002.1003321

V. Liberali

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引用次数: 3

摘要

本文给出了一个简单的外延层电阻计算和实验评估模型。该模型可用于混合信号集成电路设计的早期阶段，以估计从数字单元到模拟电路的开关噪声注入的影响。此外，所提出的模型导致一个简化的等效电路，可用于快速spice级串扰效应的模拟。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Evaluation of epi layer resistivity effects in mixed-signal submicron CMOS integrated circuits

This paper illustrates a simple model for calculation and experimental evaluation of epi layer resistance. The model can be used during early stages of mixed-signal integrated circuit design, to estimate the effects of switching noise injection from digital cells to analog circuitry. Moreover, the proposed model leads to a simplified equivalent circuit that can be used for fast SPICE-level simulations of crosstalk effects.

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来源期刊

2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595)

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