{"title":"低功耗6位电流导向DAC，采用0.18 μm CMOS工艺","authors":"Mostafa Chakir, Hicham Akhamal, H. Qjidaa","doi":"10.1109/ISACV.2015.7106175","DOIUrl":null,"url":null,"abstract":"In our work we are interested in the design of a new architecture of Current-steering DAC Converter a 6bits, operates at 300MHz sampling rate and 1.8V supply voltage, implemented in 0.18um CMOS technology for Ultra-wideband (UWB) transceivers. This work achieves the static differential non-linearity errors (DNL) and integral non linearity errors (INL) are between 0.0583/-0.0600 LSB and 0.0397/-0.1142 LSB, respectively. The spurious free dynamic range (SFDR) at 300-MSPS remains above 60.60dB for input frequency up to 100 MHz. The Total power dissipation is 944.64 uW with 1.8V power supply. The surface of the DAC is 0.006 mm2.","PeriodicalId":426557,"journal":{"name":"2015 Intelligent Systems and Computer Vision (ISCV)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"A low power 6-bit current-steering DAC in 0.18-μm CMOS process\",\"authors\":\"Mostafa Chakir, Hicham Akhamal, H. Qjidaa\",\"doi\":\"10.1109/ISACV.2015.7106175\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In our work we are interested in the design of a new architecture of Current-steering DAC Converter a 6bits, operates at 300MHz sampling rate and 1.8V supply voltage, implemented in 0.18um CMOS technology for Ultra-wideband (UWB) transceivers. This work achieves the static differential non-linearity errors (DNL) and integral non linearity errors (INL) are between 0.0583/-0.0600 LSB and 0.0397/-0.1142 LSB, respectively. The spurious free dynamic range (SFDR) at 300-MSPS remains above 60.60dB for input frequency up to 100 MHz. The Total power dissipation is 944.64 uW with 1.8V power supply. The surface of the DAC is 0.006 mm2.\",\"PeriodicalId\":426557,\"journal\":{\"name\":\"2015 Intelligent Systems and Computer Vision (ISCV)\",\"volume\":\"78 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-03-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 Intelligent Systems and Computer Vision (ISCV)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISACV.2015.7106175\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 Intelligent Systems and Computer Vision (ISCV)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISACV.2015.7106175","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A low power 6-bit current-steering DAC in 0.18-μm CMOS process
In our work we are interested in the design of a new architecture of Current-steering DAC Converter a 6bits, operates at 300MHz sampling rate and 1.8V supply voltage, implemented in 0.18um CMOS technology for Ultra-wideband (UWB) transceivers. This work achieves the static differential non-linearity errors (DNL) and integral non linearity errors (INL) are between 0.0583/-0.0600 LSB and 0.0397/-0.1142 LSB, respectively. The spurious free dynamic range (SFDR) at 300-MSPS remains above 60.60dB for input frequency up to 100 MHz. The Total power dissipation is 944.64 uW with 1.8V power supply. The surface of the DAC is 0.006 mm2.
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